Device and method for repeatedly updating the function of a LCD monitor

ABSTRACT

A monitor control system capable of reprogramming the function of a LCD monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.

CROSS-REFERENCE TO RELATED APPLICATION

More than one reissue applications have been filed for the reissue ofU.S. Pat. No. 6,697,058. This application is a continuation reissueapplication of reissue application Ser. No. 11/361,038, filed on Feb.22, 2006, now allowed. The prior reissue application Ser. No. 11/361,038is based on U.S. application Ser. No. 10/418,435, filed on Apr. 17,2003, now U.S. Pat. No. 6,697,058. U.S. Pat. No. 6,697,058 is acontinuation-in-part of application Ser. No. 09/575,890, filed on May22, 2000, now pendingU.S. Pat. No. 6,661,411, which is acontinuation-in-part of application Ser. No. 09/414,251, filed on Oct.7, 1999, now U.S. Pat. No. 6,295,053. This application The U.S. Pat. No.6,697,058 is also a continuation-in-part of application Ser. No.09/543,008, filed on Apr. 4, 2000, now U.S. Pat. No. 6,577,301, nowallowed . The entirety of each of the above-mentioned patents is herebyincorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a device and a method for repeatedly updatingthe function of a liquid quid crystal (LCD) monitor, and moreparticularly to a device and a method for repeatedly updating thefunction of a LCD monitor by using Display Data Channel (DDC) signallines for signal transmission.

2. Description of the Related Art

In a current monitor system, particularly to a LCD monitor, a monitorcontroller must be exchanged when function modifying or debugging,resulting in high cost consumed. As to a further advanced monitorsystem, a corresponding monitor controller has a build-in read onlymemory (ROM) which is an erasable programmable read only memory. Byupdating data stored in the erasable programmable read only memory,function modification and debugging can be achieved.

Referring to FIG. 1, a conventional programmable LCD monitor with thecircuit block diagram is shown. The conventional LCD monitor has a totalof 18 VGA signal lines electrically coupled to a VGA card, whichincludes a vertical synchronous signal (Vsync) line, a horizontalsynchronous signal (Hsync) line, a serial data (SDA) line, a serialclock (SCL) line, a ground (Gnd) line, a red (R) line, a green (G) lineand a blue (B) line. During a normal operation, the LCD monitorcontroller 10 receives the VGA signals. The LCD monitor also coupled toa jumper 14 for connection to the flash ROM 20 or the erase/recordsocket 80. The flash ROM 20 stores the data used to control thedisplaying function. In addition, the LCD monitor 10 also has a panelconnector to connect to the LCD displaying panel (not shown). Usually,the monitor controller 10 controls the display panel (not shown) basedon the VGA signals. The Hsync, Vsync, SDA, SCL and R.G.B signal linesare electrically coupled to the monitor controller 10 for driving thescan and data signals to the LCD displaying panel.

When it is necessary to modify the function of the monitor system, datastored in the flash ROM 20 needs to be updated. First, the case of themonitor must be opened. Then, the first jumper 14 is used to separatethe original circuit and the rewriting pathway to the flash ROM. Andthen, a cable connected to the socket 80 to transmit the updated data.

FIG. 2 is a schematic view showing the connection of a conventional LCDmonitor system with a memory erase/record system. After the externalcasing of the monitor 100 is open, a main circuit board 110 is revealed.An erase/record socket 80 and a set of VGA signal lines 18 are laid onthe circuit board 110. The first jumper 14 is found within a jumper area22. The memory erase/record system 90 includes a ROM writer 92, acomputer system 94 and a programming monitor 96. The computer system 94controls all the operations of the ROM writer 92. Programming status ofthe operation can be observed through the programming monitor 96. Whenthe ROM writer is plugged into the erase/record socket 80 of the maincircuit board 110, memory inside the monitor can be reprogrammed by thecomputer 94 so that a different monitor function can be used.

Obviously, it is really inconvenient to update the monitor systembecause the case of the conventional monitor must be first opened, andthen the jumper has to be switched for recording the erasableprogrammable read only memory of the monitor controller 10.

As a result, it is rather inconvenience when the monitor system, such asLCD monitor, is updated because it is necessary to open the case of themonitor and to switch jumpers for recording the erasable programmableread only memory of the monitor controller 10.

SUMMARY OF THE INVENTION

The invention is to provides a device for reprogramming function of aLCD monitor, which needs not to open the case and needs no theconventional jumper. Also and, it is not necessary to include aconnector with pre-designed layout for isolating the previously originalcircuit and the rewriting pathway to the flash memory. The displayingfunction of the LCD monitor can be repeatedly updated and theinformation about on-screen display.

The present invention provides a LCD monitor control system capable ofreprogramming monitor function. The monitor control system utilizes theVGA signal lines for transmitting signals during normal operation. Thesame VGA signal lines are also used for transmitting erase/recordcommands to the monitor system and to erase/record data into an externalerasable programmable ROM.

The invention provides a device for reprogramming function of a LCDmonitor, which includes a set of video graphic adapter (VGA) signallines for transmitting a plurality of erase/record commands and aplurality of erase/record data. A signal detector is coupled to the VGAsignal lines for detecting and re-transmitting the erase/record commandsand data. An activation device is coupled to the signal detector,wherein the activation device is normally connected to a video pathway,but as soon as erase/record commands are detected, the activation deviceis switched to an erase/record pathway so that erase/record commands anddata can be re-directed. A read-only-memory (ROM) erase/record commanddecoder is coupled to the activation device via the erase/recordpathway, wherein the decoder translates the erase/record commands into aplurality of erase/read/write signals and translates the erase/recorddata into a plurality of address signals and a plurality of datasignals. A plurality of address signals, a plurality of data signals anda plurality of control signals are coupled to the ROM erase/recordcommand decoder. Consequently, data stored in the external ROM unit canbe modified, according to the address, data and erase/read/write signalscoming from the command decoder. A mode return device is coupled to theROM erase/record command decoder and the activation device. Wherein, thereprogramming status of the ROM unit can be determined from the address,data and read/write signals so that the activation device can betriggered to switch over connection from the erase/record pathway to thevideo pathway as soon as reprogramming is finished.

In the foregoing device, the signal detector further includes aninter-integrated circuit multiple address content comparator circuit,which is coupled to the VGA signal lines for comparing with a pluralityof consecutive address sequences in the erase/record data such that aset signal is transmitted when there is a match with a pre-set addresssequence. A monitor-in-system programming control flag unit is coupledto the inter-integrated circuit multiple address content comparatorcircuit for transmitting a start signal after receiving the set signal.

In the foregoing device, the activation device further includes amonitor-in-system reprogramming initialization circuit for producing aselect signal after receiving the start signal, as well as anerase/record pathway isolator for switching over connection from thevideo pathway to the erase/record pathway after receiving the selectsignal and transmitting the erase/record commands and data via theerase/record pathway.

In the foregoing device, the ROM erase/record command decoder furtherincludes an inter-integrated interface circuit for receiving andtranslating the erase/record commands and data, as well as anerase/record command decoder for receiving translated erase/recordcommands and data and outputting address, data and erase/read/writesignals.

In the foregoing device, the erase/record command decoder furtherincludes a hidden ROM for holding a program code for erase/recordcommands; a random access memory (RAM) unit for holding erase/recorddata; a central processing unit coupled to the hidden ROM, the RAM unitand the inter-integrated interface circuit. Wherein the centralprocessing unit receives the erase/record commands and data passingthrough the inter-integrated circuit interface circuit and then storesthe erase/record data in the RAM unit, while the erase/record commandsare decoded by referring to the program code in the hidden ROM and thenthe decoded commands are re-transmitted. An erase/record controlregister coupled to the central processing unit for receiving thedecoded erase/record commands and converting the erase/record commandsinto the interface control signals or erase/read/write signals, andconverting the erase/record data stored in the RAM unit into address anddata signals.

The invention further provides a system for reprogramming the functionof a liquid crystal display (LCD) monitor, which comprises anerase/record device for holding and transmitting a plurality oferase/record commands and a plurality of erase/record data. A set ofvideo graphic adapter (VGA) signal lines coupled to the erase/recorddevice for transmitting the erase/record commands and data. And, a LCDmonitor controller with a monitor-in-system programming function,wherein the LCD monitor controller is coupled to the VGA signal lines sothat the erase/record commands of the erase/record device and data arereceived from the erase/record device via the VGA signal lines, and thena plurality of address signals, a plurality of data signals, and aplurality of control signals are exported for reprogramming a ROM unit,wherein the ROM unit coupled to the LCD monitor controller via signallines for transferring the address signals, the data signals and thecontrol signals, so that data stored in the ROM unit can be modifiedaccording to the address signals and the control signals, and the datasignals coming from the LCD monitor controller.

In the forgoing invention, the LCD monitor controller withmonitor-in-system programming function includes a signal detectorcoupled to the VGA signal lines for detecting and transmitting theerase/record commands and data. An activation device is coupled to thesignal detector. Wherein the activation device is normally connected toa video pathway, but as soon as erase/record commands is detected, theactivation device is switched to an erase/record pathway so thaterase/record commands and data can be re-directed. A ROM erase/recordcommand decoder is coupled to the activation device via the erase/recordpathway, wherein the decoder translates the erase/record commands into aplurality of erase/read/write signals and translates the erase/recorddata into a plurality of address signals and a plurality of data. A modereturn device is coupled to the ROM erase/record command decoder and theactivation device. Wherein, the reprogramming status of the ROM unit canbe determined from the address, data and erase/read/write signals sothat the activation device can be triggered to switch over connectionfrom the erase/record pathway to the video pathway as soon asreprogramming is finished.

The invention also provides a method for reprogramming the function of aLCD monitor system. The method includes tapping a plurality of signalsfrom a set of video graphic adapter (VGA) signal lines to perform aplurality of consecutive address sequence comparisons with a pre-setaddress sequence. A programming mode inside the LCD monitor system istriggered when one of the tapped consecutive address sequences matchesthat of the pre-set address sequence. An erase/record command is readand it is decided what actions to take as soon as the programming modeis activated. The erase/record data is read and the erase/record data iswritten into a memory unit when the erase/record command is for a writeoperation, and then returning to the previous step. When theerase/record command demands a return to a non-programming mode, theprocess returns back to the very first step.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given hereinafter and the accompanying drawings which aregiven by way of illustration only, and thus do not limit the presentinvention, and wherein:

FIG. 1 is a block diagram showing the circuit connections of variouselements of a conventional programmable LCD monitor system;

FIG. 2 is a schematic view showing the connection of a conventional LCDmonitor system with a memory erase/record system;

FIG. 3 is a block diagram showing the circuit connections of variouselements of a programmable monitor system according to this invention;

FIG. 4 is a schematic view showing the connection of a LCD monitorsystem according to this invention with an erase/record device;

FIG. 5 is a block diagram showing the circuit connections of variousinternal elements of the LCD monitor controller according to thisinvention;

FIG. 6 is a block diagram showing the circuit connections of variousinternal elements of the signal detector according . to this invention;

FIG. 7 is a block diagram showing the circuit connections of variousinternal elements of the activation device according to this invention;

FIG. 8 is a block diagram showing the circuit connections of variousinternal elements of the ROM erase/record command decoder according tothis invention;

FIG. 9 is a block diagram showing the circuit connections of variousinternal elements of the erase/record command decoder;

FIG. 10 is a block diagram showing the circuit connections of variousinternal elements of the mode return device; and

FIG. 11 is a flow chart showing the steps for reprogramming the memoryinside a LCD monitor system of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 3, a block diagram schematically shows the circuitconnections of various elements of a programmable monitor systemaccording to this invention. The invention uses a monitor controller 180with monitor-in-system programming function to receive the VGA signals18, including Vsync, Hsync, SDA, SCL, and R.G.B. signals. The monitorcontroller 180 is also coupled to a LCD displaying panel (not shown)through a panel connector and a flash ROM 120. The VGA signals 18 areinput to the monitor controller 180, then the monitor controller 180also refers to the program stored in the flash ROM 120 to drive the LCDdisplaying panel.

When the function of driving program in the flash ROM 120 is desired tobe updated, the updated program and data can be written to the flash ROM120 without the need of opening the case of the monitor and the jumperfor switching. For example, the updated information can be input throughthe SDA and SCL signal lines. Compared to the prior art, it isunnecessary to open the case of the monitor. In other words, thefunction update of the monitor can be achieved by just using theoriginal signal lines 18.

FIG. 4 is a schematic view showing the connection of a LCD monitorsystem according to this invention with an erase/record device. The maincircuit board 210 inside a monitor 200, such as a LCD monitor, isconnected to an erase/record device 190 via the set of VGA signal lines18. To reprogram the function of the monitor, erase/record commands anderase/record data are first programmed into a computer system 194. Theerase/record commands and data are translated into an inter-integratedcircuit (IIC) interface format. The translated erase/record commands anddata are output from a parallel port VGA adapter via the set of VGAsignal lines into the ROM unit inside the monitor controller 180.

Alternatively, the erase/record device can utilize an inter-integratedcircuit (IIC) interface circuit platform. To reprogram the function ofthe monitor, erase/record commands and data are first written into thememory area of the IIC interface circuit platform. The erase/recordcommands and data are sent in the IIC interface format to the ROM insidethe monitor controller 180 directly via the VGA signal lines.

In this embodiment of the invention, the serial data line SDA and theserial clock line SCL of the VGA signal lines are used to transmiterase/record commands and data in the IIC interface format. In practice,any two of the signal lines including SDA, SCL, Hsync and Vsync can beused for transmitting erase/record commands and data in the IICinterface format.

FIG. 5 is a block diagram showing the circuit connections of variousinternal elements of the monitor controller according to this invention.The monitor controller 180, which carries a ROM with a built-in controlprogram, includes a signal detector 300, an activation device 400, a ROMerase/record command decoder 500, a mode return device 600,image-processing circuits 700, which is the circuits other than thecircuits belonging to the monitor controller 180, and a ROM unit 800.

VGA signal lines are connected to the signal detector 300. The signaldetector 300 is a device for detecting any erase/record commands anddata on the VGA signal lines. Signals are next delivered to theactivation device 400.

The activation device 400 has a video pathway and an erase/recordpathway. When erase/record commands are detected by the signal detector300, the erase/record commands and data are re-directed to the ROMerase/record command decoder 500 via the erase/record pathway by theactivation device 400. In the normal mode of operation, video signalsare re-directed to the image-processing circuits 700 via the videopathway by the activation device 400.

The ROM erase/record command decoder 500 translates the erase/recordcommands into erase/read/write signals to be used by the ROM unit 120and the erase/record data are also translated into addresses and datasignals. The translated signals are the sent to the ROM unit 120 so thatmonitor function can be modified.

The ROM erase/record command decoder 500 produces the address signals,the data signals, and the control signals and then exports the signalsto an external ROM unit (not shown), which stores a program code anddata used for performing displaying function. The external ROM can, forexample, be the flash memory or erasable programmable ROM. However, ifan updated program is desired, the program code can be erased andreprogrammed according to the address signals, data signals anderase/read/write signals picked up by the ROM unit.

The mode return device 600 is coupled to the ROM erase/record commanddecoder 500 and the activation device 400. According to address, dataand read/write signals feedback from the decoder 500, progress in thereprogramming of ROM 120 can be determined. When the reprogramming isfinished, the mode return device 600 signals to the activation device400 so that connection to the video pathway is re-established.

In the following, elements and operation of each device are described indetail.

FIG. 6 is a block diagram showing the circuit connections of variousinternal elements of the signal detector according to this invention.The inter-integrated circuit multiple address content comparator 310 ofthe signal detector 300 taps the signals on the signal line SDAcontinuously, trying to match a pre-set address sequence. When thetapped consecutive address sequence matches that of the pre-set addresssequence, a Set signal is sent to a monitor-in-system programmingcontrol flag unit 320. The transmission of a Set signal to the flag unit320 indicates that reprogramming of the monitor system is desired.Consequently, a monitor-in-system programming start MISP_START signal istransmitted to the activation device 400.

FIG. 7 is a block diagram showing the circuit connections of variousinternal elements of the activation device according to this invention.As soon as the monitor-in-system reprogramming initialization circuit410 of the activation device 400 picks up the MISP_START signal from thecontrol flag unit 320, a Select signal is transmitted to an erase/recordpathway isolator 420. On receiving the Select signal, the isolator 420switches over the connection from the video pathway to the erase/recordpathway so that erase/record commands and data signals is able to passon. FIG. 8 is a block diagram showing the circuit connections of variousinternal elements of the ROM erase/record command decoder according tothis invention. The IIC interface circuit 510 of the ROM erase/recordcommand decoder 500 picks up the erase/record commands and data from theactivation device 400. The erase/record commands and data are translatedinto an erase/record commands and data format compatible to theerase/record command decoder 520. The erase/record command decoder 520converts the translated erase/record commands and data into address,data and erase/read/write signals. These address, data anderase/read/write signals are transmitted to the ROM 120 forreprogramming.

FIG. 9 is a block diagram showing the circuit connections of variousinternal elements of the erase/record command decoder. The erase/recordcommand decoder 520 includes a hidden ROM 522, a RAM unit 526, a centralprocessing unit (CPU) 524 and an erase/record control register 528.

The hidden ROM 522 is a device for storing the program code oferase/record commands, and the RAM unit 526 is a device for storingerase/record data. The central processing unit 524 picks up thetranslated erase/record commands and data from the IIC interfacecircuit. The erase/record data is stored in the RAM unit 526. Theerase/record commands are decoded using the decoding program inside thehidden ROM 522. The decoded erase/record commands are transmitted to anerase/record control register 528 where the commands are converted intoROM interface control signals or erase/read/write signals. Theerase/record data stored in the RAM unit 526 is converted into addressand data signals by the central processing unit 524.

The erase/record command decoder 520 can also be implemented using ahardware circuit. The erase/record commands picked up from the IICcircuit are divided into different states so that the commands caneasily be converted into erase/read/write, address and data signals.

FIG. 10 is a block diagram showing the circuit connections of variousinternal elements of the mode return device. The mode return register620 of the mode return device 600 picks up feedback address, data andread/write signals from the erase/record control register 528. When theerase/record procedure is complete, a mode return signal is sent to themode return circuit 610. As soon as the mode return circuit 610 picks upthe mode return signal, a monitor-in-system programming MISP_STOP signalis issued to the activation device 400. The activation device 400immediately switches over the connection from the erase/record pathwayto the video pathway. 4

FIG. 11 is a flow chart showing the steps for reprogramming the ROMinside a monitor system of this invention. First, the monitor systemmonitors incoming signals repeatedly to check for anything abnormal.Nothing happens in the normal or the video transmission mode. Whensomething abnormal is sensed by the monitor system, signals on the VGAsignal lines are tapped and a consecutive address sequence is comparedwith a pre-set address sequence. If the tapped address does not matchthe pre-set address, the monitor system returns to a normal mode.However, if there is a match between the tapped address sequence and thepre-set address sequence, the monitor system enters a reprogrammingmode. The incoming erase/record commands are checked by the monitorsystem. If the erase/record command demands that the system perform amemory write operation, erase/record data are written into the ROM unitinside the monitor controller. Thereafter, the next erase/record commandis read. On the other hand, if the erase/record command demands a returnto the normal mode of operation, the monitor system returns to thenormal mode and mode checking is again carried out.

In summary, the invention provides a monitor control system capable ofreprogramming the function of a LCD monitor. The monitor control systemutilizes the VGA signal lines for signal transmission in normaloperation and the same VGA signal lines in the modification of datainside the erasable programmable ROM of a monitor controller in thereprogramming mode. The original cable used by the VGA card can be usedto rewrite a program used by the LCD monitor controller without openingthe case and no need of the jumper. Also and, the related on-screendisplay information can also be updated.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A device for reprogramming the function of a liquid crystal display(LCD) monitor, comprising: a set of video graphic adapter (VGA) signallines for transmitting a plurality of erase/record commands and aplurality of erase/record data; a signal detector coupled to the VGAsignal lines for detecting and re-transmitting the erase/record commandsand data; an activation device coupled to the signal detector, whereinthe activation device is normally connected to a video pathway, but assoon as erase/record commands are detected, the activation device isswitched to an erase/record pathway so that erase/record commands anddata can be re-directed; a read-only-memory (ROM) erase/record commanddecoder connected to the activation device via the erase/record pathway,wherein the decoder translates the erase/record commands into aplurality of control signals and translates the erase/record data into aplurality of address signals and a plurality of data signals; aplurality of signal lines for transferring the control signals, theaddress signals, and the data signals to an external ROM unit, wherein acontent of the ROM unit can be modified according to the controlsignals, the address signals, and the data signals; and a mode returndevice coupled to the ROM erase/record command decoder and theactivation device, wherein the reprogramming status of the ROM unit canbe determined from the address, data and read/write signals so that theactivation device can be triggered to switch over connection from theerase/record pathway to the video pathway as soon as reprogramming isfinished.
 2. The device of claim 1, wherein the erase/record commandsand data come from an erase/record device that couples to the VGA signallines.
 3. The device of claim 2, wherein the erase/record device is acomputer platform that sends the erase/record commands and data in aninter-integrated circuit interface format via a parallel port VGAadapter.
 4. The device of claim 2, wherein the erase/record device is aninter-integrated circuit interface circuit platform for transmittingerase/record commands and data in an inter-integrated circuit interfaceformat.
 5. The device of claim 1, wherein the signal detector furtherincludes: an inter-integrated circuit multiple address contentcomparator circuit coupled to the VGA signal lines for comparing with aplurality of consecutive address sequences in the erase/record data suchthat a set signal is transmitted when there is a match with a pre-setaddress sequence; and a monitor-in-system programming control flag unitcoupled to the inter-integrated circuit multiple address contentcomparator circuit for transmitting a start signal after receiving theset signal.
 6. The device of claim 1, wherein the activation devicefurther includes: a monitor-in-system reprogramming initializationcircuit for producing a select signal after receiving the start signal;and an erase/record pathway isolator for switching over connection fromthe video pathway to the erase/record pathway after receiving the selectsignal and transmitting the erase/record commands and data via theerase/record pathway.
 7. The device of claim 1, wherein the ROMerase/record command decoder further includes: an inter-integratedinterface circuit for receiving and translating the erase/recordcommands and data; and an erase/record command decoder for receivingtranslated erase/record commands and data and outputting address, dataand erase/read/write signals.
 8. The device of claim 7, wherein theerase/record command decoder further includes: a hidden ROM for holdinga program code for erase/record commands; a random access memory (RAM)unit for holding erase/record data; a central processing unit coupled tothe hidden ROM, the RAM unit and the inter-integrated interface circuit,wherein the central processing unit receives the erase/record commandsand data passing through the inter-integrated circuit interface circuitand then stores the erase/record data in the RAM unit, while theerase/record commands are decoded by referring to the program code inthe hidden ROM and then the decoded commands are re-transmitted; and anerase/record control register coupled to the central processing unit forreceiving the decoded erase/record commands and converting theerase/record commands into the interface control signals orerase/read/write signals, and converting the erase/record data stored inthe RAM unit into address and data signals.
 9. The device of claim 7,wherein the erase/record command decoder is a hardware circuit thatseparates each erase/record command picked up by the inter-integratedcircuit into a plurality of states for ease of decoding and converts theerase/record commands and data into erase/read/write, address and datasignals.
 10. The device of claim 1, wherein the mode return devicefurther includes: a mode return control register for receiving theaddress, data and erase/read/write signals and producing a mode returnsignal as soon as a reprogramming operation is finished; and a modereturn circuit coupled to the mode return control register and theactivation device for sending a stop signal to the activation deviceafter receiving the mode return signal so that the activation deviceswitches over connection from the erase/record pathway back to the videopathway.
 11. The device of claim 1, wherein the external ROM unitcomprises a flash ROM unit.
 12. The device of claim 1, wherein theexternal ROM unit comprises an erasable programmable ROM unit.
 13. Asystem for reprogramming the function of a liquid crystal display (LCD)monitor, comprising: an erase/record device for holding and transmittinga plurality of erase/record commands and a plurality of erase/recorddata; a set of video graphic adapter (VGA) signal lines coupled to theerase/record device for transmitting the erase/record commands and data;and a LCD monitor controller with a monitor-in-system programmingfunction, wherein the LCD monitor controller is coupled to the VGAsignal lines so that the erase/record commands of the erase/recorddevice and data are received from the erase/record device via the VGAsignal lines, and then a plurality of address signals, a plurality ofdata signals, and a plurality of control signals are exported forreprogramming a ROM unit, wherein the ROM unit coupled to the LCDmonitor controller via signal lines for transferring the addresssignals, the data signals and the control signals, so that data storedin the ROM unit can be modified according to the address signals and thecontrol signals, and the data signals coming from the LCD monitorcontroller.
 14. The system of claim 13, wherein the erase/record deviceis a computer platform that sends the erase/record commands and data inan inter-integrated circuit interface format via a parallel port VGAadapter.
 15. The system of claim 13, wherein the erase/record device isan inter-integrated circuit interface circuit platform for transmittingerase/record commands and data in an inter-integrated circuit interfaceformat.
 16. The system of claim 13, wherein the LCD monitor controllerwith monitor-in-system programming function includes: a signal detectorcoupled to the VGA signal lines for detecting and transmitting theerase/record commands and data; an activation device coupled to thesignal detector, wherein the activation device is normally connected toa video pathway, but as soon as erase/record commands is detected, theactivation device is switched to an erase/record pathway so thaterase/record commands and data can be re-directed; a ROM erase/recordcommand decoder connected to the activation device via the erase/recordpathway, wherein the decoder translates the erase/record commands into aplurality of erase/read/write signals and translates the erase/recorddata into a plurality of address signals and a plurality of datasignals; and a mode return device coupled to the ROM record commanddecoder and the activation device, wherein the reprogramming status of aROM unit can be determined from the address, data and erase/read/writesignals so that the activation device can be triggered to switch overconnection from the erase/record pathway to the video pathway as soon asreprogramming is finished.
 17. The system of claim 16, wherein thesignal detector further includes: an inter-integrated circuit multipleaddress content comparator circuit coupled to the VGA signal lines forcomparing with a plurality of consecutive address sequences in theerase/record data such that a set signal is transmitted when there is amatch with a pre-set address sequence; and a monitor-in-systemprogramming control flag unit coupled to the inter-integrated circuitmultiple address content comparator circuit for transmitting a startsignal after receiving the set signal.
 18. The system of claim 16,wherein the activation device further includes: a monitor-in-systemreprogramming initialization circuit for producing a select signal afterreceiving the start signal; and an erase/record pathway isolator forswitching over connection from the video pathway to the erase/recordpathway after receiving the select signal and transmitting theerase/record commands and data via the erase/record pathway.
 19. Thesystem of claim 16, wherein the ROM erase/record command decoder furtherincludes: an inter-integrated interface circuit for receiving andtranslating the erase/record commands and data; and an erase/recordcommand decoder for receiving translated erase/record commands and dataand outputting address, data and erase/read/write signals.
 20. Thesystem of claim 19, wherein the erase/record command decoder furtherincludes: a hidden ROM for holding a program code for erase/recordcommands; a random access memory (RAM) unit for holding erase/recorddata; a central processing unit coupled to the hidden ROM, the RAM unitand the inter-integrated interface circuit, wherein the centralprocessing unit receives the erase/record commands and data passingthrough the inter-integrated circuit interface circuit and then storesthe erase/record data in the RAM unit, while the erase/record commandsare decoded by referring to the program code in the hidden ROM afterwhich the decoded commands are re-transmitted; and an erase/recordcontrol register coupled to the central processing unit for receivingthe decoded erase/record commands and converting the erase/recordcommands into the interface control signals or erase/read/write signals,and converting the erase/record data stored in the RAM unit into addressand data signals.
 21. The system of claim 19, wherein the erase/recordcommand decoder is a hardware circuit that separates each erase/recordcommand picked up by the inter-integrated circuit into a plurality ofstates for ease of decoding and converts the erase/record commands anddata into erase/read/write, address and data signals.
 22. The system ofclaim 16, wherein the mode return device further includes: a mode returncontrol register for receiving the address, data and read/write signalsand producing a mode return signal as soon as a reprogramming operationis finished; and a mode return circuit coupled to the mode returncontrol register and the activation device for sending a stop signal tothe activation device after receiving the mode return signal so that theactivation device switches connection from the erase/record pathway backto the video pathway.
 23. The system of claim 13, wherein the ROM unitinside the monitor controller is a flash ROM unit.
 24. The system ofclaim 13, wherein the ROM unit comprises an erasable programmable ROMunit.
 25. A method for reprogramming the function of a liquid crystaldisplay (LCD) monitor system, comprising the steps of: tapping aplurality of signals from a set of video graphic adapter (VGA) signallines to perform a plurality of consecutive address sequence comparisonswith a pre-set address sequence; triggering a programming mode insidethe LCD monitor system when one of the tapped consecutive addresssequences matches that of the pre-set address sequence; reading anerase/record command and deciding what actions to take as soon as theprogramming mode is activated; reading in erase/record data and writingthe erase/record data into a memory unit when the erase/record commandis for a write operation, and then returning to the previous step; andreturning to the very first step when the erase/record command demands areturn to a non-programming mode.
 26. The method of claim 25, whereinreprogramming starts only when the LCD monitor system is not operatingin a normal mode.
 27. The method of claim 25, wherein the LCD monitorsystem continues to operate in a normal video transmission mode when thetapped consecutive address sequence does not match any pre-set addresssequence.
 28. A device for reprogramming the function of a display,comprising: a set of video signal lines for transmitting a plurality oferase/record commands and a plurality of erase/record data; a signaldetector coupled to the video signal lines for detecting andre-transmitting the erase/record commands and data; an activation andcommand decoder device coupled to the signal detector, wherein theactivation device is normally connected to a video pathway, but afterthe erase/record commands are detected, the activation device isswitched to an erase/record pathway so that the erase/record data can bere-directed, wherein the activation and command decoder translates theerase/record commands into a plurality of control signals and translatesthe erase/record data into a plurality of data signals; a plurality ofsignal lines for transferring the control signals and the data signalsto a ROM unit, wherein a content of the ROM unit is modified accordingto the control signals and the data signals.
 29. The device of claim 28,wherein the erase/record commands and data come from an erase/recorddevice that couples to the video signal lines.
 30. The device of claim29, wherein the erase/record device is a computer platform that sendsthe erase/record commands and data in an inter-integrated circuitinterface format via a video port.
 31. The device of claim 29, whereinthe erase/record device is an inter-integrated circuit interface circuitplatform for transmitting erase/record commands and data in aninter-integrated circuit interface format.
 32. The device of claim 28,wherein the signal detector further includes: an inter-integratedcircuit address content comparator circuit coupled to the video signallines for comparing with an address in the erase/record data such that aset signal is transmitted when there is a match with a pre-set address;and a monitor-in-system programming control flag unit coupled to theinter-integrated circuit address content comparator circuit fortransmitting a start signal after receiving the set signal.
 33. Thedevice of claim 28, wherein the activation and command decoder devicefurther includes: a monitor-in-system reprogramming initializationcircuit for producing a select signal after receiving the start signal;and an erase/record pathway isolator for switching over connection fromthe video pathway to the erase/record pathway after receiving the selectsignal and transmitting the erase/record commands and data via theerase/record pathway.
 34. The device of claim 28, wherein the activationand command decoder device further includes: an inter-integratedinterface circuit for receiving and translating the erase/recordcommands and data; and an erase/record command decoder for receivingtranslated erase/record commands and data and outputting address, dataand erase/read/write signals.
 35. The device of claim 34, wherein theerase/record command decoder further includes: a hidden ROM for holdinga program code for erase/record commands; a random access memory (RAM)unit for holding erase/record data; a central processing unit coupled tothe hidden ROM, the RAM unit and the inter-integrated interface circuit,wherein the central processing unit receives the erase/record commandsand data passing through the inter-integrated circuit interface circuitand then stores the erase/record data in the RAM unit, while theerase/record commands are decoded by referring to the program code inthe hidden ROM and then the decoded commands are re-transmitted; and anerase/record control register coupled to the central processing unit forreceiving the decoded erase/record commands and converting theerase/record commands into the interface control signals orerase/read/write signals, and converting the erase/record data stored inthe RAM unit into address and data signals.
 36. The device of claim 34,wherein the erase/record command decoder is a hardware circuit thatseparates each erase/record command picked up by the inter-integratedcircuit into a plurality of states for ease of decoding and converts theerase/record commands and data into erase/read/write, address and datasignals.
 37. The device of claim 28, wherein the video signal linescomprise video graphic adapter (VGA) signal lines.
 38. The device ofclaim 28, wherein the video signal lines comprise digital visualinterface (DVI) signal lines.
 39. The device of claim 28, wherein thevideo signal lines comprise high definition multimedia interface (HDMI)signal lines.
 40. The device of claim 28, wherein the video signal linescomprise component video lines.
 41. The device of claim 28, wherein thevideo signal lines comprise S-video lines.
 42. The device of claim 28,wherein the external ROM unit comprises a flash ROM unit.
 43. The deviceof claim 28, wherein the external ROM unit comprises an erasableprogrammable ROM unit.
 44. A system for reprogramming the function of adisplay, comprising: an erase/record device for holding and transmittinga plurality of erase/record commands and a plurality of erase/recorddata; a set of video signal lines coupled to the erase/record device fortransmitting the erase/record commands and data; and a displaycontroller with a programming function, wherein the display controlleris coupled to the video signal lines so that the erase/record commandsof the erase/record device and data are received from the erase/recorddevice via the video signal lines, and then a plurality of data signalsand a plurality of control signals are exported for reprogramming a ROMunit, wherein the ROM unit coupled to the display controller via signallines for transferring the data signals and the control signals, so thatdata stored in the ROM unit are modified according to the controlsignals and the data signals coming from the display controller.
 45. Thesystem of claim 44, wherein the erase/record device is a computerplatform that sends the erase/record commands and data in aninter-integrated circuit interface format via a video port.
 46. Thesystem of claim 44, wherein the erase/record device is aninter-integrated circuit interface circuit platform for transmittingerase/record commands and data in an inter-integrated circuit interfaceformat.
 47. The system of claim 44, wherein the display controller withmonitor-in-system programming function includes: a signal detectorcoupled to the video signal lines for detecting and transmitting theerase/record commands and data; an activation device coupled to thesignal detector, wherein the activation device is normally connected toa video pathway, but after the erase/record commands is detected, theactivation device is switched to an erase/record pathway so thaterase/record commands and data can be re-directed; a command decoderconnected to the activation device via the erase/record pathway, whereinthe decoder translates the erase/record commands into a plurality oferase/read/write signals and translates the erase/record data into aplurality of data signals; and a mode return device coupled to thecommand decoder and the activation device, wherein the reprogrammingstatus of a ROM unit can be determined from the data anderase/read/write signals so that the activation device can be triggeredto switch over connection from the erase/record pathway to the videopathway after reprogramming is finished.
 48. The system of claim 47,wherein the signal detector further includes: an inter-integratedcircuit address content comparator circuit coupled to the video signallines for comparing with an address in the erase/record data such that aset signal is transmitted when there is a match with a pre-set address;and a monitor-in-system programming control flag unit coupled to theinter-integrated circuit address content comparator circuit fortransmitting a start signal after receiving the set signal.
 49. Thesystem of claim 47, wherein the activation device further includes: amonitor-in-system reprogramming initialization circuit for producing aselect signal after receiving the start signal; and an erase/recordpathway isolator for switching over connection from the video pathway tothe erase/record pathway after receiving the select signal andtransmitting the erase/record commands and data via the erase/recordpathway.
 50. The system of claim 47, wherein the command decoder furtherincludes: an inter-integrated interface circuit for receiving andtranslating the erase/record commands and data; and an erase/recordcommand decoder for receiving translated erase/record commands and dataand outputting address, data and erase/read/write signals.
 51. Thesystem of claim 50, wherein the erase/record command decoder furtherincludes: a hidden ROM for holding a program code for erase/recordcommands; a random access memory (RAM) unit for holding erase/recorddata; a central processing unit coupled to the hidden ROM, the RAM unitand the inter-integrated interface circuit, wherein the centralprocessing unit receives the erase/record commands and data passingthrough the inter-integrated circuit interface circuit and then storesthe erase/record data in the RAM unit, while the erase/record commandsare decoded by referring to the program code in the hidden ROM afterwhich the decoded commands are re-transmitted; and an erase/recordcontrol register coupled to the central processing unit for receivingthe decoded erase/record commands and converting the erase/recordcommands into the interface control signals or erase/read/write signals,and converting the erase/record data stored in the RAM unit into addressand data signals.
 52. The system of claim 50, wherein the erase/recordcommand decoder is a hardware circuit that separates each erase/recordcommand picked up by the inter-integrated circuit into a plurality ofstates for ease of decoding and converts the erase/record commands anddata into erase/read/write, address and data signals.
 53. The system ofclaim 47, wherein the mode return device further includes: a mode returncontrol register for receiving the address, data and read/write signalsand producing a mode return signal after a reprogramming operation isfinished; and a mode return circuit coupled to the mode return controlregister and the activation device for sending a stop signal to theactivation device after receiving the mode return signal so that theactivation device switches connection from the erase/record pathway tothe video pathway.
 54. The device of claim 44, wherein the video signallines comprise video graphic adapter (VGA) signal lines.
 55. The deviceof claim 44, wherein the video signal lines comprise digital visualinterface (DVI) signal lines.
 56. The device of claim 44, wherein thevideo signal lines comprise high definition multimedia interface (HDMI)signal lines.
 57. The device of claim 44, wherein the video signal linescomprise component video lines.
 58. The device of claim 44, wherein thevideo signal lines comprise S-video lines.
 59. The system of claim 44,wherein the ROM unit inside the monitor controller is a flash ROM unit.60. The system of claim 44, wherein the ROM unit comprises an erasableprogrammable ROM unit.
 61. A method for reprogramming the function of adisplay system, comprising the steps of: tapping a plurality of signalsfrom a set of video signal lines to perform an address comparison with apre-set address; triggering a programming mode inside the display systemwhen one of the tapped address matches that of the pre-set address;reading an erase/record command and deciding what actions to take afterthe programming mode is activated; reading in erase/record data andwriting the erase/record data into a memory unit when the erase/recordcommand is for a record operation.
 62. The method of claim 61, whereinreprogramming starts only when the display system is not operating in anormal mode.
 63. The method of claim 61, wherein the display systemcontinues to operate in a normal video transmission mode when the tappedaddress does not match any pre-set address.